/* $Id$ */
/* vim: set filetype=verilog ts=8 sw=4 tw=132: */
/*****************************************************************************
 
              (c) Copyright 1987 - 2012,  VIA Technologies, Inc.       
                            ALL RIGHTS RESERVED                            
                                                                     
 This design and all of its related documentation constitutes valuable and
 confidential property of VIA Technologies, Inc.  No part of it may be
 reproduced in any form or by any means   used to make any transformation
 / adaptation / redistribution without the prior written permission from the
 copyright holders. 
 
------------------------------------------------------------------------------

  DESCRIPTION:

  FEATURES:

  TODO:

  AUTHORS:
     Shawn Fang
    
------------------------------------------------------------------------------
                             REVISION HISTORY
    $Log$

*****************************************************************************/
module select_PC
    (
	input  [31:0] M_valA,
	input  [31:0] W_valM,
	input  [31:0] predPC,
	input  [3:0] f_icode,
	input  [3:0] M_icode,
	input  [3:0] W_icode,
	input  [2:0]f_stat,
	input  [2:0]m_stat,
	input  [31:0] m_pc,
	input  M_cnd,
	output reg  [31:0] f_pc
    );


    always @ (M_icode,W_icode,M_valA,W_valM,predPC,M_cnd,f_stat,m_stat,m_pc,f_icode)
    begin
//	if(m_stat!=`SAOK)
//	    f_pc<=m_pc;
//	else 
         if(f_stat==`SHLT)
	    if(M_icode==`IJXX && ~M_cnd)
	    f_pc<=M_valA;
	    else
	    f_pc<=f_pc;
	else
	begin
	if(M_icode==`IJXX && ~M_cnd)
	    f_pc<=M_valA;
	else if(W_icode==`IRET)
	    f_pc<=W_valM;
	else if(f_icode==`IHALT)
	    f_pc<=f_pc;
	else
	    f_pc<=predPC;
	end
    end


endmodule


